From an optical backbone technology, 10 Gbit Ethernet is rapidly diversifying into many other media and uses. This evolution shows up clearly in new 10 Gbit silicon, of which the most recent example is a 26-port switch from Fujitsu.

The impetus for the change is most frequently blamed on the increasing use of mobile media by those ultimate consumer creatures, the 14-25-year-old affluent set. (Never mind that this group is reportedly fatiguing and reducing their use of video-based services, or that we may be heading deeper into a consumer recession that will curtail the growth of all such media toys.) Delivering rich media puts bandwidth pressure on backbone optical networks and, increasingly, on access networks. A less obvious point Fujitsu makes is that these media clients are also putting bandwidth pressure on the server farms that source the content into the network. All of these areas, according to the company, are under pressure to move to 10 Gbit links, but each is reacting in its own ways.

In the case of access networks, the pressure may mean increased use of 10 Gbit passive optical networks (PONs.) In the case of blade servers and clusters, the need for speed is expressing itself in another way: the 802.3ap (or KR, if you prefer) 10 Gbit-over-backplane link. In both cases, since the switching task may require aggregation/disaggregation of many streams with different QoS requirements, there is need for considerable intelligence in flow control.

Fujitsu is attempting to respond to the needs of both worlds with a single chip, the MB86C69RBC 26-port 10 Gbit Ethernet switch chip. As the name strongly suggests, the chip includes 26 10 Gbit Ethernet ports. These ports all have on-chip multi-rate PHYs, capable of driving XAUI/CX4/KX4 connections, XFI-compatible connections, or 1000Kx connections, and directly driving KR backplane traces. Thus all ports can handle a wide variety of backplane, copper cable, and optical-transducer connections.

The number 26, if you are curious, comes from Fujitsu's survey of the needs of ATCA clusters, backbone switches, blade switches, and top-of-rack switching arrangements, in which 26 channels appeared to be about the right number for most full-up configurations.

The 26 ports are all led, through input buffers, to a large, fast, shared memory structure that serves as both non-blocking switch and output buffer. Switch control is done on-chip by a local microengine, under advice from a pair of 10/100/1Gbit management ports. Flow control inside the chip is handled by a system of transmit tokens that allow transfers from the input buffers to the shared memory. In this way the chip can implement congestion notification, priority pause, and L3 ACL (access control list) and forwarding, among other tricks. Naturally these functions are supported by available software.

Even though Fujitsu has deep experience in Ethernet switches with integrated PHYs, the 90 nm design was a significant challenge. "There is no way to avoid a great deal of analog design work with a large number of 10 Gbit PHYs," observes Fujitsu business unit director Asif Hazarika. "Even though our internal 90 nm process is designed specifically to reduce substrate coupling, there is still a lot of modeling, HSPICE runs, and experience—where to use trench isolation, for instance."