Description:
...data, address and control registers. Internal logic allows the SRAM togenerate a self-timed write based upon a decision which can be left untilthe end of the write cycle.The burst mode feature offers the highest level of performance to the... ...data for a single address presented to the SRAM. An internal burst addresscounter accepts the first cycle address from the processor, initiating theaccess sequence. The first cycle of output data will be pipelined for onecycle before it is available on the next rising clock edge. If burst mode... ...3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature RangesNOTES: 1.Device is selected through entire cycle; ...