Description:
...features of the BT485 are supported by the TVP3025. Section 2.4.17 gives details on TVP3025 compatibilitywith the BT485 and functions not supported. When accessing the BT485 emulation registers, only featureswhich are supported by the BT485 and have a counterpart on the TVP3025 can be utilized. If additionalTVP3025 features are to be used, they must be accessed through the TVP3025 register map.... ...If MODE1 is logic 0 when the TVP3025 is reset, the device initializes the TVP3025 register maps as specifiedin Table 2–1 and Table 2–3 and translation of the BT485 emulation registers does not take place. Also, thecursor RAM interface is set to the nonplanar access mode (TVP3025 cursor control register bit 7 = 0) withthe same operation as the TVP3020. The internal BT485 registers can subsequently be programmed via... ...The SCLK signal which is generated in the TVP3025 is intended to be directly connected to VRAM, providingthe shift clock to clock data from VRAM onto the TVP3025 pixel input port. The RCLK signal must be usedas the timing reference to clock pixel data into this port. Therefore, RCLK is typically directly tied back toLCLK, or LCLK can be a delayed version of RCLK within the timing requirements of the TVP3025. The SCLK...